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HI-8281
January 2001
GENERAL DESCRIPTION
The HI-8281 device from Holt Integrated Circuits is a silicon gate CMOS device for interfacing a 16-bit parallel data bus directly to the ARINC 429 serial bus. The device provides two receivers, an independent transmitter and line driver capability in a single package. The receiver input circuitry and logic are designed to meet the ARINC 429 specifications for loading, level detection, timing, and protocol. The transmitter section provides the ARINC 429 communication protocol and the line driver circuits provide the ARINC 429 output levels. The 16-bit parallel data bus exchanges the 32-bit ARINC data word in two steps when either loading the transmitter or interrogating the receivers. The data bus interfaces with CMOS and TTL. Timing of all the circuitry begins with the master clock input, CLK. For ARINC 429 applications, the master clock frequency is 1 MHz. Each independent receiver monitors the data stream with a sampling rate 10 times the data rate. The sampling rate is software selectable at either 1MHz or 125KHz. The results of a parity check are available as the 32nd ARINC bit. The HI-8281 examines the null and data timings and will reject erroneous patterns. For example, with a 125 KHz clock selection, the data frequency must be between 10.4 KHz and 15.6 KHz. The transmitter has a First In, First Out (FIFO) memory to store 8 ARINC words for transmission. The data rate of the transmitter is software selectable by dividing the master clock, CLK, by either 10 or 80. The master clock is used to set the timing of the ARINC transmission within the required resolution.
FEATURES
! ARINC specification 429 compatible ! Direct receiver and transmitter interface to ARINC bus in a single device. ! 16-Bit parallel data bus. ! Timing control 10 times the data rate ! Selectable data clocks ! Receiver error rejection per ARINC specification 429 ! Automatic transmitter data timing ! Self test mode ! Parity functions ! Low power ! Industrial & full military temperature ranges
PIN CONFIGURATION (Top View)
APPLICATIONS
! Avionics data communication ! Serial to parallel conversion ! Parallel to serial conversion
(See page 4-27 for additional pin configuration)
(DS8281 Rev. A)
HOLT INTEGRATED CIRCUITS 1
01/01
HI-8281
SIGNAL
VCC V+ V429DI1 (A) 429DI1 (B) 429DI2 (A) 429DI2 (B) D/R1 D/R2 SEL EN1 EN2 BD15 BD14 BD13 BD12 BD11 BD10 BD09 BD08 BD07 BD06 GND BD05 BD04 BD03 BD02 BD01 BD00 TX/R PL1 PL2 TXA(OUT) TXB(OUT) ENTX CWSTR CLK TX CLK MR SLP1.5
FUNCTION
POWER POWER POWER INPUT INPUT INPUT INPUT OUTPUT OUTPUT INPUT INPUT INPUT I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O POWER I/O I/O I/O I/O I/O I/O OUTPUT INPUT INPUT OUTPUT OUTPUT INPUT INPUT INPUT OUTPUT INPUT INPUT +5V 5%
DESCRIPTION
+12V 5% or +15V 10% -12V 5% or -15V 10% ARINC receiver 1 positive input ARINC receiver 1 negative input ARINC receiver 2 positive input ARINC receiver 2 negative input Receiver 1 data ready flag Receiver 2 data ready flag Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2) Data Bus control, enables receiver 1 data to outputs Data Bus control, enables receiver 2 data to outputs if EN1 is high Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus 0 V - both pins must be connected Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high After transmission and FIFO empty. Latch enable for byte 1 entered from data bus to transmitter FIFO. Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow PL1. Line driver output - A side Line driver output - B side Enable Transmission Clock for control word register Master Clock input Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80. Master Reset, active low Logic input to control the slope of the differential output signal. HIGH = 1.5 s
HOLT INTEGRATED CIRCUITS 2
HI-8281
FUNCTIONAL DESCRIPTION
CONTROL WORD REGISTER
The HI-8282 contains 10 data flip flops whose D inputs are connected to the data bus and clocks connected to CWSTR. Each flip flop provides options to the user as follows:
DATA BUS
ARINC 429 DATA FORMAT
The following table shows the bit positions in exchanging data with the receiver or the transmitter. ARINC bit 1 is the first bit transmitted or received. BYTE 1
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 13 12 11 10 9 31 30 32 1 2 3 4 5 6 7 8
DATA BUS PIN
BDO5
FUNCTION CONTROL
DESCRIPTION
If enabled, an internal connection is made passing 429DO and 429DO to the receiver logic inputs If enabled, ARINC bits 9 and, 10 must match the next two control word bits If Receiver 1 Decoder is enabled, the ARINC bit 9 must match this bit If Receiver 1 Decoder is enabled, the ARINC bit 10 must match this bit If enabled, ARINC bits 9 and 10 must match the next two control word bits If Receiver 2 Decoder is enabled, then ARINC bit 9 must match this bit If Receiver 2 Decoder is enabled, then ARINC bit 10 must match this bit Logic 0 enables normal odd parity and Logic 1 enables even parity output in transmitter 32nd bit CLK is divided either by 10 or 80 to obtain XMTR data clock CLK is divided either by 10 or 80 to obtain RCVR data clock
ARINC BIT
SELF TEST
0 = ENABLE
BYTE 2
DATA BUS ARINC BIT BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
BDO6
RECEIVER 1 DECODER
1 = ENABLE
BDO7
-
-
THE RECEIVERS
ARINC BUS INTERFACE
Figure 1 shows the input circuit for each receiver. The ARINC 429 specification requires the following detection levels:
BDO8
-
-
BDO9
RECEIVER 2 DECODER
1 = ENABLE
BD10
-
-
STATE ONE NULL ZERO
DIFFERENTIAL VOLTAGE +6.5 Volts to +13 Volts +2.5 Volts to -2.5 Volts -6.5 Volts to -13 Volts
BD11
-
-
BD12
INVERT XMTR PARITY XMTR DATA CLK SELECT RCVR DTA CLK SELECT
1 = ENABLE
The HI-8282 guarantees recognition of these levels with a common mode Voltage with respect to GND less than 4V for the worst case condition (4.75V supply and 13V signal level). The tolerances in the design guarantee detection of the above levels, so the actual acceptance ranges are slightly larger. If the ARINC signal is out of the actual acceptance ranges, including the nulls, the chip rejects the data.
BD13
0 = /10 1 = /80 0 = /10 1 = /80
BD14
HOLT INTEGRATED CIRCUITS 3
HI-8281
FUNCTIONAL DESCRIPTION (con't)
RECEIVER LOGIC OPERATION Figure 2 shows a block diagram of the logic section of each receiver. BIT TIMING The ARINC 429 specification contains the following timing specification for the received data: HIGH SPEED LOW SPEED 100K BPS 1% 12K -14.5K BPS 1.5 0.5 sec 10 5 sec 1.5 0.5 sec 10 5 sec 5 sec 5% 34.5 to 41.7 sec
3. Each data bit must follow its predecessor by not less than 8 samples and no more than 12 samples. In this manner the bit rate is checked. With exactly 1MHz input clock frequency, the acceptable data bit rates are as follows: HIGH SPEED DATA BIT RATE MIN DATA BIT RATE MAX 83K BPS 125K BPS LOW SPEED 10.4K BPS 15.6K BPS
BIT RATE PULSE RISE TIME PULSE FALL TIME PULSEWIDTH
4. TheWordGaptimersamplestheNullshiftregister every 10 input clocks (80 for low speed) after the last data bit of a Valid reception. If the Null is present, theWordGapcounter Is incremented. A count of 3 will enable the next reception. RECEIVER PARITY The receiver parity circuit counts Ones received, including the parity bit, ARINC bit 32. If the result is odd, then "0" will appear in the 32nd bit.
Again the HI-8282 accepts signals that meet these specifications and rejects outside the tolerances. The way the logic operation achieves this is described below: 1. Key to the performance of the timing checking logic is an accurate 1MHz clock source. Less than 0.1% error is recommended. 2. The sampling shift registers are 10 bits long and must show three consecutive Ones, Zeros or Nulls to be considered valid data. Additionally, for data bits, the One or Zero in the upper bits of the sampling shift registers must be followed by a Null in the lower bits within the data bit time. For a Null in the word gap, three consecutive Nulls must be found in both the upper and lower bits of the sampling shift register. In this manner the minimum pulse width is guaranteed.
RETRIEVING DATA
Once 32 valid bits are recognized, the receiver logic generates an End of Sequence (EOS). If the receiver decoder is enabled and the 9th and 10th ARINC bits match the control word program bits or if the receiver decoder is disabled, then EOS clocks the data ready flag flip flop to a "1", D/R1 or D/R2 (or both) will go low. The data flag for a receiver will remain low until after both ARINC bytes from that receiver are retrieved. This is accomplished by activating EN with SEL, the byte selector, low to retrieve the first byte and activating EN with SEL high to retrieve the second byte. ENI retrieves data from receiver 1 and EN2 retrieves data from receiver 2. If another ARINC word is received, and a new EOS occurs before the two bytes are retrieved, the data is overwritten by the new word.
TO PINS SEL EN D/R DECODER CONTROL BITS
MUX CONTROL
32 TO 16 DRIVER
CONTROL BIT BD14
CLOCK OPTION
CLOCK
CLK
/
LATCH ENABLE CONTROL BITS 9 & 10
32 BIT LATCH BIT COUNTER AND END OF SEQUENCE
32 BIT SHIFT REGISTER
DATA
PARITY CHECK
32ND BIT
BIT CLOCK
EOS
EOS
ONES
WORD GAP
WORD GAP TIMER
BIT CLOCK
SHIFT REGISTER
START
END
NULL
SHIFT REGISTER
SEQUENCE CONTROL
ZEROS
SHIFT REGISTER
ERROR
ERROR DETECTION
CLOCK
FIGURE 2.
RECEIVER BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS 4
HI-8281
TRANSMITTER
A block diagram of the transmitter section is shown in Figure 3.
TRANSMITTER PARITY
The parity generator counts the ONES in the 31-bit word. If the BD12 control word bit is set low, the 32nd bit transmitted will make parity odd. If the control bit is high the parity is even.
FIFO OPERATION
The FIFO is loaded sequentially by first pulsing PL1 to load byte 1 and then PL2 to load byte 2. The control logic automatically loads the 31 bit word in the next available position of the FIFO. If TX/R, the transmitter ready flag is high (FIFO empty), then 8 words, each 31 bits long, may be loaded. If TX/R is low, then only the available positions may be loaded. If all 8 positions are full, the FIFO ignores further attempts to load data.
SELF TEST
If the BD05 control word bit is set low, 429DO or 429DO become inputs to the receiver bypassing the interface circuitry.
SYSTEMOPERATION
The two receivers are independent of the transmitter. Therefore, control of data exchanges are strictly at the option of the user. The only restrictions are: 1. The received data may be overwritten if not retrieved within one ARINC word cycle. 2. The FIFO can store 8 words maximum and ignores attempts to load addition data if full. 3. Byte 1 of the transmitter data must be loaded first. 4. Either byte of the received data may be retrieved first. Both bytes must be retrieved to clear the data ready flag. 5. After ENTX, transmission enable ,goes high it cannot go low until TX/R, transmitter readyflag, goes high. Otherwise, one ARINC word is lost during transmission.
DATA TRANSMISSION
When ENTX goes high, enabling transmission, the FIFO positions are incremented with the top register loading into the data transmission shift register. Within 2.5 data clocks the first data bit appears at either 429DO or 429DO. The 31 bits in the data transmission shift register are presented sequentially to the outputs in the ARINC 429 format with the following timing: HIGH SPEED 10 Clocks 5 Clocks 5 Clocks 40 Clocks LOW SPEED 80 Clocks 40 Clocks 40 Clocks 320 Clocks
ARINC DATA BIT TIME DATA BIT TIME NULL BIT TIME WORD GAP TIME
The word counter detects when all loaded positions are transmitted and sets the transmitter ready flag, TX/R, high.
HOLT INTEGRATED CIRCUITS 5
HI-8281
LINE DRIVER OPERATION
The line driver in the HI-8281 is designed to directly drive the ARINC 429 bus. The two ARINC outputs (TXA(OUT) and TXB(OUT)) provide a differential voltage to produce a +10 volt One, a -10 volt Zero, and a 0 volt Null. The device incorporates on board zeners to translate internal CMOS levels to ARINC specified amplitudes. A logic input (SLP1.5) is provided to control the slope of the differential output signal. No additional hardware is required to control the slope. A HIGH on SLP1.5 causes a slope of 1.5 s on the ARINC outputs; a LOW on SLP1.5 causes a slope of 10 s. Timing is set by on-chip resistor and capacitor and tested to be within ARINC requirements. The HI-8281 has 37.5 ohms in series with each line driver output.
REPEATER OPERATION
Repeater mode of operation allows a data word that has been received by the HI-8281 to be placed directly into its FIFO for transmission. Repeater operation is similar to normal receiver operation. In normal operation, either byte of a received data word may be read from the receiver latches first by use of SEL input. During repeater operation however, the lower byte of the data word must be read first. This is necessary because, as the data is being read, it is also being loaded into the FIFO and the transmitter FIFO is always loaded with the lower byte of the data word first. Signal flow for repeater operation is shown in the Timing Diagrams section.
TXA(OUT)
ARINC BIT
TXB(OUT)
DATA NULL DATA NULL DATA NULL
BIT 30
BIT 31
BIT 32
WORD GAP
BIT 1 NEXT WORD
DATA BUS
VALID
tCWSET t CWHLD
CWSTR
t CWSTR
t D/R
t END/R t EN t SELEN tENSEL tENEN tDATAEN t ENDATA tSELEN tENSEL
tD/REN
DATA BUS
t DATAEN
tENDATA
HOLT INTEGRATED CIRCUITS 6
HI-8281
DATA BUS
BYTE 1 VALID
BYTE 2 VALID
tDWSET
PL1
tDWHLD
tDWSET
tDWHLD tPL12
t PL
PL2
tPL12
TX/R
t PL
tTX/R
PL2
tDTX/R tPL2EN
TX/R ENTX
t ENTX/R
ARINC BIT DATA BIT 1 ARINC BIT DATA BIT 2
t ENDAT
ARINC BIT DATA BIT 32
+5V TXA(OUT) -5V +5V TXB(OUT) -5V
+5V
-5V
tfx
+10V V DIFF (TXA(OUT) - TXB(OUT))
90% 10%
+10V
tfx
10% zero level 90%
trx
trx
one level
null level
-10V
HOLT INTEGRATED CIRCUITS 7
HI-8281
429DI
BIT 32
t END/R
D/R
tD/R
EN
tD/REN
t EN
t ENEN
t EN
t SELEN
SEL
DON'T CARE
tENSEL
DON'T CARE
tENPL
PL1
tPLEN tENPL
tSELEN
t ENSEL t PLEN
PL2
tTX/R
TX/R
tTX/REN
ENTX
tENTX/R
tENDAT
TXA(OUT) TXB(OUT) BIT 1
t DTX/R
BIT 32
t NULL
HOLT INTEGRATED CIRCUITS 8
HI-8281
Supply Voltages Vcc V+ VVoltage at pins 4, 5, 6 and 7 Voltage at pin 38 Voltage at any other pin
-0.3V to +7V Power Dissipation at 25C Plastic PLCC 20V Ceramic J-LEAD CERQUAD -20V -29V to +29V DC Current Drain per pin -0.3 to V+ +0.3V Storage Temperature Range: -0.3V to Vcc +0.3V Operating Temperature Range: (Industrial) (Military)
1.5 W, derate 10mW/C 1.0 W, derate 7mW/C 10mA -65C to +150C -40C to +85C -55C to +125C
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Vcc = 5V 5%, V+ = 12V to 15V, V- = -12V to -15V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
ARINC INPUTS Pins 4, 5, 6 & 7 ONE ZERO NULL Differential To GND To Vcc Input Sink Input Source Differential To GND To Vcc
SYMBOL
CONDITIONS
LIMITS
MIN TYP MAX
UNIT
Differential Input Voltage:
VIH VIL VNUL RI RG RH IIH IIL CI CG CH
Pins 4 to 5, 6 to 7: Common mode voltage less than 4V with respect to GND
6.5 -13.0 -2.5 12 12 12 -450
10.0 -10.0 0 27 27
13.0 -6.5 2.5
V V V K K K
Input Resistance:
Input Current: Input Capacitance: (Guaranteed but not tested)
200 Pins 4 to 5, 6 to 7 20 20 20
A A pF pF pF
BI-DIRECTIONAL INPUTS - Pins 13 - 22, 24 - 29 Input Voltage: Input Current: Input Voltage HI Input Voltage LO Input Sink Input Source VIH VIL IIH IIL 2.1 0.7 1.5 -1.5 V V A A
OTHER INPUTS - Pins 1, 8 - 12, 30, 31, 39, 40 & 43 Input Voltage: Input Current: INPUT - SLP1.5, PIN 38 Input Voltage Input Current Input Voltage HI Input Voltage LO Input Sink Input Source VIH VIL IIH IIL VIN = 0V VIN = 5V 2.1 V+ 0.5 0.1 0.1 V V A A Input Voltage HI Input Voltage LO Input Sink Input Source VIH VIL IIH IIL 3.5 0.7 10 -20 V V A
HOLT INTEGRATED CIRCUITS 9
HI-8281
Vcc = 5V 5%, V+ = 12V to 15V, V- = -12V to -15V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
LIMITS PARAMETER
ARINC OUTPUTS - Pins 35 & 36 ARINC output voltage One or zero Null ARINC output current OTHER OUTPUTS - Pins 13-22, 24-29, 32 & 34 Output Voltage: Output Current: (Bi-directional Pins) Output Current: (All Other Outputs) Output Capacitance: Operating Supply Current VCC, Pin 3: V+, Pin 37: V-, Pin 34: ICC1 IDD1 IEE1 20 16 16 mA mA mA Logic "1" Output Voltage Logic "0" Output Voltage Output Sink Output Source Output Sink Output Source VOH VOL IOL IOH IOL IOH CO IOH = -1.5mA IOL = 1.8mA VOUT = 0.4V VOUT = VCC - 0.4V VOUT = 0.4V VOUT = VCC - 0.4V 2.7 0.4 3.0 1.5 3.6 1.5 15 V V mA mA mA mA pF VDOUt VNOUT IOUT no load and magnitude at pin
" " " " " "
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
4.50 -0.25 80
5.00
5.50 0.25
V V mA
HOLT INTEGRATED CIRCUITS 10
HI-8281
Vcc = 5V, V+=12V to 15V, V- = -12V to -15V,GND = 0V, TA = Oper. Temp. Range and fclk = 1MHz +0.1% with 60/40 duty cycle
PARAMETER CONTROL WORD TIMING Pulse Width - CWSTR Setup - DATA BUS Valid to CWSTR HIGH Hold - CWSTR HIGH to DATA BUS Hi-Z RECEIVER TIMING Delay - Start ARINC 32nd Bit to D/R LOW: High Speed Low Speed Delay - D/R LOW to EN L0W Delay - EN LOW to D/R HIGH Setup - SEL to EN L0W Hold - SEL to EN HIGH Delay - EN L0W to DATA BUS Valid Delay - EN HIGH to DATA BUS Hi-Z Pulse Width - EN1 or EN2 Spacing - EN HIGH to next EN L0W FIFO TIMING Pulse Width - PL1 or PL2 Setup - DATA BUS Valid to PL HIGH Hold - PL HIGH to DATA BUS Hi-Z Spacing - PL1 or PL2 Delay - PL2 HIGH to TX/R LOW TRANSMISSION TIMING Spacing - PL2 HIGH to ENTX HIGH Delay - 32nd ARINC Bit to TX/R HIGH Spacing - TX/R HIGH to ENTX L0W LINE DRIVER OUTPUT TIMING Delay - ENTX HIGH to TXA(OUT) or TXB(OUT): High Speed Delay - ENTX HIGH to TXA(OUT) or TXB(OUT): Low Speed Line driver transition differential times: (High Speed, Pin 38 - Logic 1) high to low low to high high to low low to high
SYMBOL MIN
LIMITS TYP MAX
UNITS
tCWSTR tCWSET tCWHLD
130 140 0
ns ns ns
tD/R tD/R tD/REN tEND/R tSELEN tENSEL tENDATA tDATAEN tEN tENEN 240 50 0
16 128 200 20 50 200 30
s s ns ns ns ns ns ns ns ns
tPL tDWSET tDWHLD tPL12 tTX/R
200 110 20 0 840
ns ns ns ns ns
tPL2EN tDTX/R tENTX/R
0 400 0
s ns ns
tENDAT tENDAT tfx trx tfx trx 1.0 1.0 5.0 5.0 1.5 1.5 10 10
27 216 2.0 2.0 15 15
s s s s s s
(Low Speed, Pin 38 = Logic 0)
HOLT INTEGRATED CIRCUITS 11
HI-8281
Vcc = 5V, V+ = 12V to 15V, V- = -12V to -15V,GND = 0V, TA= Oper. Temp. Range and fclk = 1MHz +0.1% with 60/40 duty cycle
LIMITS PARAMETER
REPEATER OPERATION TIMING Delay - EN LOW to PL LOW Hold - PL HIGH to EN HIGH Delay - TX/R LOW to ENTX HIGH Master Reset Pulse Width ARINC Data Rate and Bit Timing tENPL tPLEN tTX/REN tMR 0 0 0 400 1% ns ns ns ns
SYMBOL MIN TYP MAX
UNITS
HOLT INTEGRATED CIRCUITS 12
HI-8281
ADDITIONAL HI-8281 PIN CONFIGURATION
(See page 4-23 for additional pin configuration)
ORDERING INFORMATION
PART NUMBER
HI-8281PJI HI-8281PJT HI-8281CJI HI-8281CJT
PACKAGE DESCRIPTION 44 PIN PLASTIC J LEAD 44 PIN PLASTIC J LEAD 44 PIN CERQUAD J LEAD 44 PIN CERQUAD J LEAD
TEMPERATURE RANGE
-40C TO +85C -55C TO +125C -40C TO +85C -55C TO +125C
FLOW
I T I T
BURN IN
NO NO NO NO
LEAD FINISH SOLDER SOLDER SOLDER SOLDER
HOLT INTEGRATED CIRCUITS 13
HI-8281 PACKAGE DIMENSIONS
inches (millimeters)
44-PIN PLASTIC J-LEAD PLCC
PIN NO. 1 .045 x 45 PIN NO. 1 IDENT .045 x 45
PACKAGE TYPE:
.050 .005 (1.27 .127) .690 .005 (17.526 .127) SQ. .653 .004 (16.586 .102) SQ. .031 .005 (.787 .127) .017 .004 (.432 .102)
SEE DETAIL A
.009 .011
.172 .008 (4.369 .203) .610 .020 (15.494 .508) DETAIL A
.015 .002 (.381 .051) .020 MIN (.508 ) R .025 .045
44-PIN CERQUAD J-LEAD
Package Type:
2 1 44 43
.688 .005 (17.475 .127) MAX. SQ.
.620 .012 (15.748 .305)
.650 .010 (16.510 .254) SQ. .039 .005 (.990 .127) .019 .002 (.483 .051) .200 MAX. (5.080) .100 .007 .050 TYP. (2.540 .178) (1.270)
HOLT INTEGRATED CIRCUITS 14

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